$ C258 32820
$ CY7C258 32820
$ P258 32820
00000 : PROM [ 4 ]
32768 : SELECT 25 [ AR | AP ]   : SELECT 24 [ AR | AP ]
	  : SELECT 23 [ AR | AP ]   : SELECT 19 [ AR | AP ]
	  : SELECT 18 [ AR | AP ]   : SELECT 17 [ AR | AP ]
	  : SELECT 16 [ AR | AP ]   : SELECT 15 [ AR | AP ]
	  : SELECT 29 [ AR | AP ]   : SELECT 30 [ AR | AP ]
	  : SELECT 31 [ AR | AP ]   : SELECT 32 [ AR | AP ]
	  : SELECT 33 [ AR | AP ]   : SELECT 34 [ AR | AP ]
	  : SELECT 35 [ AR | AP ]   : SELECT 36 [ AR | AP ]
	  : COMMENT Register Initialization word *
32784 : IREG  2 [ REG | COMB ]  :  FB  2 [ PIN | Q ]
	  : IREG  3 [ REG | COMB ]  :  FB  3 [ PIN | Q ]
	  : IREG  4 [ REG | COMB ]  :  FB  4 [ PIN | Q ]
	  : IREG  5 [ REG | COMB ]  :  FB  5 [ PIN | Q ]
	  : IREG  6 [ REG | COMB ]  :  FB  6 [ PIN | Q ]
	  : IREG  9 [ REG | COMB ]  :  FB  9 [ PIN | Q ]
	  : IREG 10 [ REG | COMB ]  :  FB 10 [ PIN | Q ]
	  : IREG 11 [ REG | COMB ]  :  FB 11 [ PIN | Q ]
	  : IREG 12 [ REG | COMB ]  :  FB 12 [ PIN | Q ]
	  : IREG 13 [ REG | COMB ]  :  FB 13 [ PIN | Q ]
	  : IREG 14 [ REG | COMB ]  :  FB 14 [ PIN | Q ]
	  : COMMENT Inputs 2..6,9..14 Register ByPass and Path Select *
32806 : FUSES 0 *
	  : COMMENT Cs/h bit *
32807 : IREG 27 [ REG | COMB ]  :  REG 37 [ D | COMB_default ]
	  : IPOL 27 [  AL |  AH ]
	  : COMMENT Output Enable macrocell control bits *
32810 : IREG  1 [ REG | COMB ]  :  REG 38 [ D | COMB_default ]
	  : COMMENT Initialization macrocell control bits *
32812 : REG 25 [ D | COMB ]  :  REG 24 [ D | COMB ]  :  REG 23 [ D | COMB ]
	  :	REG 19 [ D | COMB ]  :  REG 18 [ D | COMB ]  :  REG 17 [ D | COMB ]
	  :	REG 16 [ D | COMB ]  :  REG 15 [ D | COMB ]
	  : COMMENT Outputs 25..23,19..15 Bypass Muxes *
" -------------
$ C259 32828
$ CY7C259 32828
$ P259 32828
00000 : PROM [ 4 ]
32768 : SELECT 42 [ AR | AP ]   : SELECT 41 [ AR | AP ]
      : SELECT 40 [ AR | AP ]   : SELECT 39 [ AR | AP ]
      : SELECT 38 [ AR | AP ]   : SELECT 37 [ AR | AP ]
      : SELECT 34 [ AR | AP ]   : SELECT 33 [ AR | AP ]
      : SELECT 32 [ AR | AP ]   : SELECT 31 [ AR | AP ]
      : SELECT 27 [ AR | AP ]   : SELECT 26 [ AR | AP ]
      : SELECT 25 [ AR | AP ]   : SELECT 24 [ AR | AP ]
      : SELECT 23 [ AR | AP ]   : SELECT 21 [ AR | AP ]
      : COMMENT Register Initialization word *
32784 : IREG  5 [ REG | COMB ]  :  FB  5 [ PIN | Q ]
      : IREG  6 [ REG | COMB ]  :  FB  6 [ PIN | Q ]
      : IREG  7 [ REG | COMB ]  :  FB  7 [ PIN | Q ]
      : IREG  9 [ REG | COMB ]  :  FB  9 [ PIN | Q ]
      : IREG 10 [ REG | COMB ]  :  FB 10 [ PIN | Q ]
      : IREG 13 [ REG | COMB ]  :  FB 13 [ PIN | Q ]
      : IREG 15 [ REG | COMB ]  :  FB 15 [ PIN | Q ]
      : IREG 16 [ REG | COMB ]  :  FB 16 [ PIN | Q ]
      : IREG 17 [ REG | COMB ]  :  FB 17 [ PIN | Q ]
      : IREG 18 [ REG | COMB ]  :  FB 18 [ PIN | Q ]
      : IREG 19 [ REG | COMB ]  :  FB 19 [ PIN | Q ]
      : COMMENT Inputs 5..7,9,10,13,15..19 Register ByPass and Path Select *
32806 : FUSES 0 *
      : COMMENT Cs/h bit *
32807 : IREG  3 [ REG | COMB ]  :  REG 45 [ D | COMB_default ]
      : IPOL  3 [  AL |  AH ]
      : COMMENT Output Enable macrocell control bits *
32810 : IREG  2 [ REG | COMB ]  :  REG 46 [ D | COMB_default ]
      : COMMENT Initialization macrocell control bits *
32812 : REG 42 [ D | COMB ]  :  REG 41 [ D | COMB ]  :  REG 40 [ D | COMB ]
      : REG 39 [ D | COMB ]  :  REG 38 [ D | COMB ]  :  REG 37 [ D | COMB ]
      : REG 34 [ D | COMB ]  :  REG 33 [ D | COMB ]  :  REG 32 [ D | COMB ]
      : REG 31 [ D | COMB ]  :  REG 27 [ D | COMB ]  :  REG 26 [ D | COMB ]
      : REG 25 [ D | COMB ]  :  REG 24 [ D | COMB ]  :  REG 23 [ D | COMB ]
      : REG 21 [ D | COMB ]
      : COMMENT Outputs 42..37,34..31,27..23,21 Bypass Muxes *
$ !EOF!
