         Release Note for Taishan/Caesar2/Caesar2 Server Bootcode Firmware
         =================================================================
              5784m, 5764m, 5723

----------------------------
Version 3.34 ---- 3/25/08  (Do not use this bootcode for A steps devices)
----------------------------      

1. Problem:
	 PHY access corruption. (CQ34229, CQ34234, CQ24229)
   Cause:
     Driver and Bootcode accessing PHY registers at the sametime.
   Fix:
     Bootcode Version 3.32, 3.33 are trying to resolve CQ34229 and CQ34234.
     But they also introduced CQ24229. Version 3.34 will resolve CQ34229 
     and CQ34234 by avoiding accessing PHY registers when driver is loaded. 
     Bootcode will read Phy ID and setup GPHY APD in Phase 2. To avoid the
     Phy access corruption, bootcode will read the PHY ID in Phase 1 and only
     setup GPHTY APD when driver is not loaded.  When driver is loaded, driver
     will set up GPHY APD if it is enabled in NVRAM.


----------------------------
Version 3.33 ---- 3/19/08  (Do not use this bootcode for A steps devices)
----------------------------      

1. Problem:
	 Intresting packet WOL not working when ASF is enabled. (CQ34339, CQ34358)
   Cause:
     The change in version 3.32 causes reset signature not inverted when ASF
     is enabled.
   Fix:
   	 Invert reset signature in phase 1 when ASF is enabled.

----------------------------
Version 3.32 ---- 3/18/08  (Do not use this bootcode for A steps devices)
----------------------------      

1. Problem:
	 PHY access corruption. (CQ34229, CQ34234)
   Cause:
     Driver and Bootcode accessing PHY registers at the sametime.
   Fix:
   	 Invert reset signature at the end of phase 2 init to make sure all
   	 PHY access by the bootcode are done.

----------------------------
Version 3.31 ---- 2/15/08  (Do not use this bootcode for A steps devices)
----------------------------      

1. Extended L1 entry time to 4ms to address CQ33880 by writing Reg 0x7d28 with 0x182FFFA. 

----------------------------
Version 3.30 ---- 2/14/08  (Do not use this bootcode for A steps devices)
----------------------------      

1. Updated the L1 ASPM Timer setting function.
   Bootcode will issue a read after each write to Reg 0x7d28 and 0x7d00.

----------------------------
Version 3.29 ---- 2/13/08  (Do not use this bootcode for A steps devices)
----------------------------      
   
1. Switching the Core Clock to 12.5MHz before setting L1 ASPM Timer.

----------------------------
Version 3.28 ---- 2/12/08  (Do not use this bootcode for A steps devices)
----------------------------      
   
1. Extended L1 ASPM Timer by writing Reg 0x7d28 with 0x18262FA.


----------------------------
Version 3.27 ---- 2/11/08  (Do not use this bootcode for A steps devices)
----------------------------      
   
1. Disable CQ27862 workaround by the following script.
   1. Write 4900 0x48401
   2. Write 4904 0xCE08
   3. Write 4910 0x18

----------------------------
Version 3.26 ---- 1/29/08  (Do not use this bootcode for A steps devices)
----------------------------      
   
1. Do not clear bit 16 of Reg 0x3600 when GRC reset.  Only clear this bit right before PHY reset when enabling 10mb receive only mode.

----------------------------
Version 3.25 ---- 1/25/08  (Do not use this bootcode for A steps devices)
----------------------------      
   
1. Remove the workaround for Taishan when ASF or PXE is enabled.
   Added the following script.
 
   if asf is enabled do
   1. write 3624 0
   2. setbit 3600 28
   3. setbit 3628 13
 
   if asf is diabled do
   1. clearbit 3628 13
   2. clearbit 3600 28
   
2. Enable 10mb receive only mode by default when driver is absent.

----------------------------
Version 3.24 ---- 1/22/08  (Do not use this bootcode for A steps devices)
----------------------------      
   
1. Change the sequence of register write to enable 10mb rx only mode by default.  
   Old Sequence:
    setbit x3600 16 
    mwrite 17 0f08 
    mwrite 15 0201
     
   New Sequence:
    mwrite 17 0f08 
    mwrite 15 0201
    setbit x3600 16  

----------------------------
Version 3.23 ---- 1/21/08  (Do not use this bootcode for A steps devices)
----------------------------      
   
1. Removed all workaround for A steps devices.

2. Set the default state of the Phy Auto Power Down configuration bit to be enabled.

3. Set bit 16 of register 0x3600 be for enable gphy auto early-dac-mode.

4. Set bit 1 and 3 of register 0x3670 by default.

5. Set the default value of register 3618 to 0x171700.  

----------------------------
Version 3.22 ---- 1/17/08  (Last version of bootcode to support A steps devices)
----------------------------      
   
1. Make Phy Auto Power Down configuration controlled by the NVRAM Phy Auto Power Down configuration bit.
   Set the default state of the Phy Auto Power Down configuration bit to be disabled.
   Phy Auto Power Down configuration is done in Phase 2 of bootcode after initPhy().
   
2. Removed NVRAM configuration bits and code that allows the user to enable/disable clkreq, L0s & L1ASPM. 


----------------------------
Version 3.21 ---- 1/10/08 
----------------------------      
   
1. Clear bit 16 of register offset 0x7d00 for B0 step by hard coding the value to 0x38841fff.

----------------------------
Version 3.20 ---- 1/09/08 
----------------------------      
   
1. Clear bit 29 of register offset 0x68A4 and bit 16 of register offset 0x7d00 for B0 step.

----------------------------
Version 3.19 ---- 1/07/08 
----------------------------      
   
1. Enabled CQ 31680 workaround for 5784m, 5764m and 5723 B0.

2. Applied the follow script to 5784m, 5764m and 5723 B0.
    mii_write(0x1c, 0xA821); < This enable GPHY APD
    mii_write(0x1c, 0x941D); < This enables DLL Power Down in APD by clearing bit 2 in GPHY Register 1C at Shadow 0x5

    mii_write(0x17, 0x0F08); < Select Expansion Register 08
    mii_write(0x15, 0x0201); < Set low-power 10BASE-T mode for interoperability fix

3. Set APD_SlowClock_Enable (Bit 13) at Reg offset 0x3600 for 5784m, 5764m and 5723 B0.

4. Set MI_MODE_CORE_CLOCK_SPEED_62MHZ (Bit 15) at Reg offset 0x454 for 5784m, 5764m and 5723 B0.

----------------------------
Version 3.18 ---- 12/19/07 
----------------------------      
   
1. Problem:
     The default value of Reg 0xD8 had been changed and cause register test to fail at 0xDC.
   Cause:
     The default state of Clkreq, ASPM_L0 and ASPM_L1 setting at register 0xD8 was changed based on the NVRAM configuration bits.
   Fix:
     Modified the NVRAM configuration bits default state of Clkreq, ASPM_L0 and ASPM_L1 to preserve 
     the default state of Clkreq, ASPM_L0 and ASPM_L1 setting in Reg 0xD8.

2. Making Clkreq, ASPM_L0 and ASPM_L1 NVRAM configuration bits applicable to all steps.
     
----------------------------
Version 3.17 ---- 12/17/07 
----------------------------      

1. Reduced code size to less then 8Kbytes.
     
2. Added new configuration bits to support 5764M, 5784M and 5723 B0 step.
   Added Link Idle Mode, Clkreq, ASPM_L0 and ASPM_L1 configuration bits for 5764M, 5784M and 5723 B0.
   These new bits can be set via b57diag that support 5764M, 5784M and 5723 B0. 

----------------------------
Version 3.16 ---- 12/11/07 
----------------------------      

1. Problem CQ#33000:
     5784m, 5764m and 5723 failed PCI SIG electrical compliance test with 50ohm termination applied.
   Cause:
     The device was using high power mode for the receiver detect.
   Workaround:
     Via MDIO write new rcvr detect threshold.
     1.  write 44c 241f8610
     2.  write 44c 24150477
     
2. Problem CQ#32740:
     5764M (STM45PE20) - powering the system up/down causes NVRAM corruption when ASF is enabled.
   Cause:
     The SPI Clk DIV has been modified to speed up the nvram data access. This modification works for
     Atmel flash but fails on the ST flash.
   Fix:
     Undo this modification.
     
     
----------------------------
Version 3.15 ---- 12/07/07 
----------------------------      

1. Eliminate the mii_read() function in Phase I bootcode to save more code space
   PHY ID in Shared Memory at offset 0xb74 will be updated in Phase II of bootcode instead of Phase I. 
   So that we can eliminate the mii_read() function in Phase I bootcode to save more code space.

----------------------------
Version 3.14 ---- 12/05/07 
----------------------------      

1. Modified code to get the chip rev from CPMU register instead of PCI Cfg Register since there 
   will be no access to PCI CFG registers when running in Vaux Mode.

2. Modified code to setup the device to use the low power mode for the receiver detect.

----------------------------
Version 3.13 ---- 11/30/07 
----------------------------      

1. Cleaned up unused functions from source code to make room for future grow.

2. Added A2 step support.

3. Problem:
     PXE does not work on 5784m, 5764m, 5723 with bootcode version 3.12.
   Cause:
     Due to adding code to workaround CQ32116, the phase 1 bootcode size increase over 4k and corrupted the PXE code.
   Fix:
     Moving CQ32447, CQ31190 and CQ31680 workaound to phase 2 bootcode to resolve the issue.


----------------------------
Version 3.12 ---- 11/20/07 
----------------------------      
1. Problem CQ 32116:
      Parity Check 2 - during boot sequence of iscsi boot NX1.
    Workaround:
      Disabled LowPower_EnergyDetect Mode, LinkSpeed Mode, LinkAware Mode and AirplaneMode when it is a NIC and PXE enable.
      In addition, reduce the number of byte to read from NVRAM to 32 bytes when service proc_expansion_rom_event() to speed up the boot sequence of iscsi boot.

----------------------------
Version 3.11 ---- 11/13/07 
----------------------------      
1. Problem CQ 32447:
      BCM5784M: Taishan-A0 Failed File-Copy-Compare with Clkreq Enabled.
    Workaround:
      Enabled CQ30808 and CQ30888 by setting bits 4:2 in Register 4910 for 5784m, 5764m, 5723 A0/A1.  
      This is done by writing to register 4910 with a value of 0x1C.

----------------------------
Version 3.10 ---- 11/12/07 
----------------------------      
1. Problem:
      Device rev checking function was broken and result in workarounds for 5784m, 5764m and 5723 A0/A1 may be applied to B0 step.
   
   Fix:
      Fixed device rev checking function to ensure that A0/A1 workaround will not be applied to B0 step.
      
----------------------------
Version 3.09 ---- 11/07/07 
----------------------------      
1. Problem CQ 32245:
      Cable Sense Mode for 5784M is not disabled by default in boot code version 3.08
   Cause:
      Outdated config file was used when building version 3.08.
   Fix:
      Rebuild 3.08 bootcode with up to date config file and update the bootcode version to 3.09.
      
2. Problem:
      Some functions that did not gain access right before writing to CPMU registers.
   Fix:
      Added code request and release access right before and after writing to CPMU registers. 
      
3. update release note for V3.08      
      
----------------------------
Version 3.08 ---- 11/05/07 
----------------------------      
1. Problem CQ 32154:
      If ASF is enabled and no cable is plugged into the 5764M NIC, it will not be 
      recognized in B57Diag.
    Workaround:
      Disable Link Aware Mode and Link Speed Power Mode when ASF is enabled.

2. Problem CQ32021:
      5764m Ethernet (RJ-45) LED turned on with bootcode v3.07 when ASF enable (b57diag) which should be not.
   Workaround:
     When ASF is enabled, it requires having full clock speed. 
     Enable LS and LA will prevent the device run at full clock speed.  
     Therefore enable LS and LA when ASF is enabled is not a right setting.
     It may affect the behavior of the LED. The workaround for this issue is 
     to disable Link Aware Mode and Link Speed Power Mode when ASF is enabled.

3. Undo CQ31830 fix.  Keep Airplane mode in CPMU Ctrl reg in default state.

4. Problem:
     Vaux power still on after chip shut down in NIC
   Cause:
     A bug in the bootcode that did not cut the Vaux power when shut down.
   Fix:
     Cut Vaux power when shut down device.
     
5. Updated CQ31179 workaround to reduce more code size.

----------------------------
Version 3.07 ---- 10/26/07 
----------------------------      
1. Changed shutdown code for 5784m, 5764m, 5723 to use CPMU to force 
   chip into Low Power State.

2. Problem CQ32111:
     Missing handshaking logic among the CPMU, GPHY, and GMAC_CLKGEN causing the core clock 
     to stop in D0u with Airplane power mode enabled or Link Aware Mode with 
     Link Speed Power mode disabled.
   Workaround:
     Modified 5784m, 5764m, 5723 to turn off GPHY auto-powerdown mode.

3. PHY initialization settings added for 5784m, 5764m, 5723.

4. Problem CQ31815: 
     Taishan - Blue screen on boot if no network cable attached.
   Workaround:        
     Disable CPMU GPHY APD Debounce Low Logic on 5784m, 5764m, 5723.

5. Problem CQ31619:
     BCM5784: Taishan A0 failed DMA Write Engine Lock Up when Link Speed Mode 
     Enabled with 10Mb Traffic and Core clock is 1.5MHz.
   Workaround:
     Enabled Link Speed Power Mode when Link Aware/CableSense modes are enabled.

6. Problem CQ31702:
     Taishan: Activity LED not working in GPHY led mode.
   Workaround:
     Applied blick rate override workaround on 5784m, 5764m, 5723.

7. Changed LED mode to MAC mode for 5784m, rev. A0/A1.

8.  Problem CQ 31680:
     Fails with Clock Req testing with PLLPOWER down and RefClk parked
    Workaround:
     Changing PCIE Serdes PLL Bandwidth from 9MHz to 5-6MHz to allow the PCIE 
     Serdes to tolerate noisy PCIE Reference Clock.  
     In addition, Selecting the VDDR Bias instead of the Band-Gap BIAS Circuitry



----------------------------
Version 3.06 ---- 10/17/07 
----------------------------      
1. Added modifications to L1 workaround for 5784m, 5764m and 5723 L1 Recovery Time.

2. Problem CQ31619: 
     Taishan A0 failed DMA Write Engine Lock Up when Link Speed Mode Enabled with 10Mb Traffic 
     and Core clock is 1.5MHz.
   Workaround:
     Added modifications to CPMU clock policy registers to prevent 5784m, 5764m and 5723 DMA 
     Write Engine Lock Up.

3. Modified code to correctly set 5764m and 5723 CPMU clock policy registers in ASF mode.

----------------------------
Version 3.05 ---- 10/16/07 
----------------------------      
1.  Enabled Airplane mode in CPMU Ctrl reg. to fix CQ31830.

----------------------------
Version 3.04 ---- 10/08/07 
----------------------------      
1.  Change the default state of energy detect (cable sense mode) to disable.
    Boot code enables low power mode with energy detect (cable sense mode), 
    link aware power mode and link speed power mode in 0x3600 upon power up.  
    Since there is a priority between the LPED and LA power modes, as long as LPED is enabled, 
    the CPMU will never go into the LA mode.
    
----------------------------
Version 3.03 ---- 9/29/07 
----------------------------

1.  Problem CQ 31179:
      Timer modifications to support CPMU Link Aware Mode for 5784m, 5764m and 5723.
    Workaround:
      Service patch to program the timer pre-scaler according to the core clock speed is added to workaround this issue.  
      This patch will only run when driver is absent.
      
2.  Problem CQ 31190:
      FW workaround to reduce 5784m, 5764m and 5723 L1 Recovery Time.
    Workaround:
       Init patch is added to program the PCI-E Serdes to reduce 5784m, 5764m and 5723 L1 recovery time.

----------------------------
 Version 3.02 ---- 7/30/07 
----------------------------
1. Fixed VPD registers offset.

----------------------------
 Version 3.01 ---- 6/29/07 
----------------------------
1. Removed workaround for CQ#22173,CQ#22176,CQ#22178,CQ#22180,CQ#22254.

   The problem with PCIE link polarity is fixed in 5784m and 5764m. 
   
2. Removed workaround for CQ#27044
   
   It is not applicable in the 65nm SerDes in 5784m and 5794m.   
   
   
3. Removed workaround for CQ#28997.

   The problem with the Serial Number corruption is fixed in 5784m and 5764m. 
   
----------------------------
 Version 3.00 ---- 6/26/07 
----------------------------
1. Initial engineering release

   This is a branch of 5787 v3.26.
   Removed CQ#14315 workaround.
   Removed CQ#25114 workaround.
   Removed 130nm PHY workaround.
   

