      Taishan, Caesar II and Caesar Server Selfboot Patch For Chip Rev. B0
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            5784m, 5764m and 5723

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Version  2.18  (Format 1)
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1. Extended L1 entry time to 4ms to address CQ33880 by writing Reg 0x7d28 with 0x182FFFA. 

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Version  2.17  (Format 1)
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1. Updated the L1 ASPM Timer setting function.
   Bootcode will issue a read after each write to Reg 0x7d28 and 0x7d00.


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Version  2.16  (Format 1)
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1. Switching the Core Clock to 12.5MHz before setting L1 ASPM Timer.

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Version  2.15  (Format 1)
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1. Extended L1 ASPM Timer by writing Reg 0x7d28 with 0x18262FA.

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Version 2.14  (Format 1)
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1. Disable CQ27862 workaround by the following script.
   1. Write 4900 0x48401
   2. Write 4904 0xCE08
   3. Write 4910 0x18


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Version 2.13  (Format 1)
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1. Do not clear bit 16 of Reg 0x3600 when GRC reset.  Only clear this bit right before PHY reset when enabling 10mb receive only mode.

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Version 2.12  (Format 1)
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1. Enable 10mb receive only mode by default when driver is absent.

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Version 2.11  (Format 1)
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1. Change the sequence of register write to enable 10mb rx only mode by default.  
   Old Sequence:
    setbit x3600 16 
    mwrite 17 0f08 
    mwrite 15 0201
     
   New Sequence:
    mwrite 17 0f08 
    mwrite 15 0201
    setbit x3600 16  

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Version 2.10  (Format 1)
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1. Removed NVRAM configuration bits and code that allows the user to enable/disable clkreq, L0s & L1ASPM. 

2. Set bit 16 of register 0x3600 be for enable gphy auto early-dac-mode.

3. Set bit 1 and 3 of register 0x3670 by default.

4. Set the default value of register 3618 to 0x171700.  

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Version 2.09  (Format 1) 
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1. Set Phy Auto Power Down according to the NVRAM setting.

2. Moved Phy Auto Power Down setup to ICP_DEVICE_INIT patch.

3. Set Phy Auto Power Down NVRAM setting default state to Enable.

4. Fixed incorrect offset when accessing register.
   Used register offset from CPU view instead of HOST view.
   e.g. "0xc0003600" instead of "0x3600".


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Version 2.08  (Format 1) 
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1. Recode ICP_POST_PHY_INIT patch.
   The patch may not set the low-power 10BASE-T mode of the phy correctly with the device under new process.

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Version 2.07  (Format 1) 
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1. Clear bit 16 of register offset 0x7d00 for B0 step by hard coding the value to 0x38841fff.

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Version 2.06  (Format 1) 
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1. Moved code from ICP_REVISION_INIT patch to ICP_POST_REVISION_INIT patch for the patch to take effect.

2. Added the follow code to ICP_POST_REVISION_INIT patch to save code space even though it does not below to this patch.
   Clear bit 29 of register offset 0x68A4 and bit 16 of register offset 0x7d00 for B0 step.
            
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Version 2.05  (Format 1) 
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1. Enabled CQ 31680 workaround for 5784m, 5764m and 5723 B0.

2. Applied the follow script to 5784m, 5764m and 5723 B0.
    mii_write(0x1c, 0xA821); < This enable GPHY APD
    mii_write(0x1c, 0x941D); < This enables DLL Power Down in APD by clearing bit 2 in GPHY Register 1C at Shadow 0x5

    mii_write(0x17, 0x0F08); < Select Expansion Register 08
    mii_write(0x15, 0x0201); < Set low-power 10BASE-T mode for interoperability fix

3. Set APD_SlowClock_Enable (Bit 13) at Reg offset 0x3600 for 5784m, 5764m and 5723 B0.

4. Set MI_MODE_CORE_CLOCK_SPEED_62MHZ (Bit 15) at Reg offset 0x454 for 5784m, 5764m and 5723 B0.

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Version 2.04  (Format 1) 
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1. Added Phy Init script to ICP_POST_PHY_INIT patch. 
    Features : 1) Increase HPF corner by 9% 
	           2) Disable LPF filter
	           3) Increase line driver current by 40% for better TX distortion	 
               4) Set 10BASE-T low power for interoperability

2. Added CQ 31680 workaround to ICP_PCIE_SERDES_INIT patch.

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Version 2.03  (Format 1) 
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1. Problem :
     hwinfo_0 at offset 0xd2c of shared memory posted incorrect information for 5764m.
   Cause:
     hwinfo_0 was updated with an incorrect Group_ID for 5764m.
   Fix:
     ICP_REVISION_INIT patch has been added to correct the Group ID at offset 0xd2c in shared memory.

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Version 2.02  (Format 1) 
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1. Set Clkreq, ASPM_L0 and ASPM_L1 configuration bits default to enable.

2. Set Link Idle Mode configuration bit default to disable.
             
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Version 2.01  (Format 1) 
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1. Problem CQ#33000:
     5784m, 5764m and 5723 failed PCI SIG electrical compliance test with 50ohm termination applied.
   Cause:
     The device was using high power mode for the receiver detect.
   Workaround:
     Via MDIO write new rcvr detect threshold.
     1.  write 44c 241f8610
     2.  write 44c 24150477
     
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Version 2.00  (Format 0)
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Initial ASIC B0 patch release    
